1. Field of the Invention
The present invention relates to a chip (e.g. IO circuit) with programmable function and method of implementing the same, and more particularly, to a chip capable of realizing different I/O functions by only altering the layouts of a metal connection layer and method of implementing the same.
2. Description of the Prior Art
Various electronic circuits formed in semiconductor chips have become a foundation of the information technology industry. Consequently, to reduce the cost and time of designing and manufacturing semiconductor chips has become a key target for the semiconductor manufacturers.
The manufacturing procedures of semiconductor chips are as follows. First, the circuit layouts are designed according to different functional requirements, and corresponding masks are defined according to the design of the circuit layouts. Then, different semiconductor layers are consecutively formed on the wafer by respectively using different masks so as to define different layout layers (such as doped regions, polysilicon layers, oxide layers, or different metal layers). These layout layers form various circuits so as to implement different circuit functions of each circuit in the chip.
If the chip fails to achieve expected performance, the circuit layouts must be redesigned to improve the circuit function. With the adjustment of the circuit layouts, however, the layout design of the masks must be changed correspondingly. The modification of the masks undoubtedly increases the cost and time of manufacturing and designing chips. In other words, if fewer masks are redesigned for implementing different circuit functions, the cost and time of manufacturing the chips are dramatically reduced.
Please refer to FIG. 1, which is a schematic diagram of a conventional layout design of a chip. Generally, chips include kernel (core) circuits and peripheral interface circuits, where a kernel circuit is responsible for executing main functions, such as logical operations, and the peripheral interface circuits include different I/O circuits for outputting the operation results of the kernel circuit, or for receiving input signals and converting the input signals into signals suitable for the kernel circuit. As shown in FIG. 1, a chip 10 includes a kernel circuit 12, and a plurality of I/O circuits 14A to 14C which function as interface circuits.
Generally speaking, different chips require different I/O functions. In most cases, even a single chip requires different I/O pins for implementing different I/O functions. For example, the Schmidt trigger function (noise-proof function) is a basic requirement for some certain kinds of chips. In addition, some chips can only tolerate I/O signals with a certain power, driving current, or response speed (such as slew rate). Accordingly, the I/O circuits of these kinds chips have to be particularly designed. For example, the I/O circuit with a high driving current can be realized by designing a larger doped region (doped well).
In order to design and realize various kinds of I/O functions, a database, in which different layout designs for various sub-circuit cells are recorded, is typically adopted to support different I/O functions where necessary. When a user (layout designer) has to realize a circuit with a certain I/O function, a sub-circuit cell layout, which fulfills the requirement of the certain I/O function, can be obtained by accessing the database. Therefore, the layout designer can easily realize the layout of the chip by applying the like layout design. FIG. 1 illustrates a case of applying a database 16. The database 16 includes different layout designs of various sub-circuit cells 18A to 18C (here 18A to 18C are only explanatory examples, a typical database may have more than three hundred layout designs), and each sub-circuit cell 18A to 18C has a different layout design and transistor arrangement so as to support different I/O functions. For example, the transistors of the sub-circuit cell 18B may have a larger doped region and a broader channel so as to provide a larger driving current than the sub-circuit cell 18A. The sub-circuit cell 18C supports the Schmidt trigger function with its complex transistor arrangement. In addition, each sub-circuit cell 18A to 18C has a transmission terminal 19A to 19C for respectively connecting to the kernel circuit 12.
Assuming that the I/O functions that the I/O circuits 14A to 14C require can be respectively implemented by the sub-circuit cells 18A to 18C, the layout designer just needs to respectively apply the layout designs of the sub-circuit cells 18A to 18C to the I/O circuits 14A to 14C, and couple the kernel circuit 12 with the transmission terminals 19A to 19C of each sub-circuit cell 18A to 18C respectively by connection layouts. Accordingly, in this way the kernel circuit 12 and the I/O circuits 14A to 14C are configured.
However, conventional circuit design is not perfect, and one of the disadvantages is that numerous masks have to be redesigned. For example, if the layout designer finds the I/O circuit 14B has unexpected noise, and attempts to replace the I/O circuit 14B with other noise-proof I/O circuits, the layout designer can retrieve other suitable layout designs in the database 16. Nevertheless, the problem is that once the layout design of the I/O circuit is changed, the layouts of related masks have to be correspondingly changed. Consequently, the time and cost of manufacturing and designing the chips cannot be reduced.
Please refer to FIG. 2, which is a schematic diagram of another conventional layout design of a chip. Likewise, various layout designs contained in a database 26 are used for implementing I/O circuits 24A to 24C in a chip 20. What differs from the previous example is that each sub-circuit cell of the database 26 has a limited programmable ability. This means each sub-circuit cell can perform different I/O functions. For example, the sub-circuit cell 28A can be selected to provide two different I/O functions. In addition to a transmission terminal 29A, the sub-circuit cell 28A further includes a control terminal 27A for receiving a programming signal. If the control terminal 27A receives a programming signal consistent with a first predetermined value (for example, the voltage of the programming signal is kept at a first constant), the sub-circuit cell 28A will provide the first I/O function (such as providing a smaller driving current). On the other hand, if the control terminal 27A receives a programming signal consistent with a second predetermined value, the sub-circuit cell 28A will provide the second I/O function (such as providing a larger driving current). Similarly, the sub-circuit cell 28B can provide another limited programmable ability by adopting another transistor arrangement. In addition to a transmission terminal 29B, the sub-circuit cell 28B further includes two control terminals 27B and 27C for selecting the required I/O function. Normally, the control terminal enables or disables some circuits of a sub-circuit cell so that the sub-circuit cell can selectively provide more than one I/O function.
When different I/O functions need to be realized in the chip 20, the layout designer has to apply available layout designs in the database 26, and design proper control terminals for programming the required I/O function to each sub-circuit cell. For example, assuming that the I/O circuits 24A and 24B require different I/O functions, and these two I/O functions happen to be two I/O functions that the sub-circuit cell 28A supports, the layout designer can easily realize these two I/O functions by applying the layout design of the sub-circuit cell 28A. Certainly, in addition to the connection layouts between the kernel circuit 22 and the I/O circuits 24A and 24B, the layout designer has to further arrange two connection layouts 23A and 23B of the control terminals so that the I/O circuits 24A and 24B can respectively receive different control signals. Normally, the control terminal can receive the control signal coming from the kernel circuit, or alternatively the control terminal can be connected to a DC bias voltage (such as Vdd or Vgnd).
However, if other I/O circuits require different I/O functions that the sub-circuit cell 28A does not support, the layout designer still has to select other available sub-circuit cells capable of supporting the required I/O functions.
Although the conventional layout design shown in FIG. 2 can realize different I/O functions with the same sub-circuit cell, this layout design still has the same disadvantage. Assuming that an I/O circuit is beyond the expected performance, the layout designer has to choose other sub-circuit cells in the database 26. Since each sub-circuit cell has different transistor arrangements, related masks have to be redesigned if different sub-circuit cells are selected. If the required I/O function happens to be the other I/O function that the same sub-circuit cell supports, only the connection layout of the control terminal has to be redesigned. Regardless, the control terminal of each sub-circuit cell unavoidably occupies the circuit layout area, and this makes the circuit layout more complicated.